1. Field of the Invention
The present invention relates to a charge pump circuit contained in a PLL frequency synthesizer and in particular, to a charge pump circuit capable of a high speed operation at a low voltage.
2. Description of the Related Art
For example, a mobile communication system such as a global positioning system (GPS) including a mobile telephone unit and car navigation of employs phase locked loop (PLL) frequency synthesizer. Such a PLL frequency synthesizer is disclosed in Japanese Patent Publication No. 7-143002. The PLL frequency synthesizer disclosed here includes: a reference counter; a crystal oscillator; a frequency divider; a phase comparator; a charge pump circuit; a loop filter as a low pass filter; and a voltage control oscillator (VCO).
The PLL frequency synthesizer described in the aforementioned publication operates as follows. When a reference signal based on an oscillation signal of a predetermined frequency is output by the reference counter to the phase comparator, the phase comparator compares the reference signal with a comparison signal and outputs phase difference pulse signals xcfx86R, xcfx86P according to the comparison result, to the charge pump circuit.
In response to high level/low level of the phase difference pulse signals xcfx86R and xcfx86P, the charge pump circuit operates a switch unit consisting of a pair of built-in transistors. By the operation of this switch unit, if an ascending voltage signal is output, the loop filter is charged, and if a descending voltage signal is output, the loop filter is discharged. The loop filter flattens the ascending/descending voltage signals from the charge pump circuit and outputs it to the voltage control oscillator, as a control voltage signal from which a high frequency pulse component has been removed.
The voltage control oscillator outputs a frequency signal having frequency corresponding to a voltage value of the control voltage signal from the loop filter, so as to send back the signal to the frequency divider. The aforementioned operation is repeated until the frequency signal of the voltage control oscillator is locked to several times of the frequency of the reference signal.
When using the aforementioned conventional PLL frequency synthesizer in a mobile communication system, with increase of the number of telephone units and variety of uses, it becomes necessary to operate from the ordinary kHz band to the high frequency of MHz band as well as to reduce spurious caused by the phase comparison frequency signal and to increase the synchronization processing speed. In order to realize this, the charge pump circuit should have a function to rapidly respond to the phase comparator of high-speed operation and to charge/discharge the loop filter at a high speed.
It is therefore an object of the present invention to provide a charge pump circuit capable of operating at a high speed with a low power source voltage and increasing the synchronization processing speed.
The charge pump circuit according to the present invention comprises: a first transistor connected between a first power source and an output node; and a second transistor connected between a second power source and said output node; wherein the first and the second transistors are controlled in response to a first signal and a second signal so as to control a current flowing into and out of the output node, said charge pump circuit further comprising: a first switch circuit connected between a first input node through which the first signal is input and a base of the first transistor and controlling the first transistor in response to the first signal; and a second switch circuit connected between a second input node through which the second signal is input and a base of the second transistor and controlling the second transistor in response to the second signal; wherein the first and the second transistors and transistors contained in the first and the second switch circuits are all NPN transistors.
In the charge pump circuit according to the present invention, the first and the second transistors and the transistors used in the first and the second switch circuit are all NPN transistors using electrons as career. Accordingly, it is possible to realize a high-speed operation at a low voltage in response to a high-speed phase comparison signal, and to charge/discharge the loop filter at the subsequent stage, enabling a high-speed synchronization processing. Moreover, since NPN transistors of identical configuration are formed on a single substrate, it is possible to simplify the production procedure and the circuit configuration and reduce the production cost as well as reduce the lay-out area on the semiconductor chip and reduce the circuit size in comparison to the case when MOS transistors and bipolar transistors are used in combination.
Here, it is preferable that the first switch circuit comprise: a third transistor having a collector connected to the first power source via a first resistor and to the base of the third transistor, which base is connected to the base of the first transistor; a fourth transistor having a collector connected to the collector of the third transistor, an emitter connected to the second power source, and a base connected to the first input node; and a first bias circuit inserted between the third transistor and the second power source. In this case, it is possible to realize the first switch circuit with a simple circuit configuration.
Moreover, it is preferable that the first bias circuit be constituted by a plurality of transistors connected so as to operate as diodes. In this case, it is possible to realize the first bias circuit with a simple circuit configuration.
Alternatively, it is also preferable that the first bias circuit be constituted by: a bias transistor having a collector connected to the emitter of the third transistor and an emitter connected to the second power source; a second resistor connecting the base and collector of the bias transistor; and a third resistor connecting the base and emitter of the bias transistor. In this case also, it is possible to realize the first bias circuit with a simple circuit configuration.
Moreover, it is preferable that the second switch circuit comprise: a second bias circuit connected to the first power source via the second resistor; a fifth transistor having a collector connected to the second bias circuit, an emitter connected to the second power source, and a base connected to the second input node; a sixth transistor having a collector connected to the second bias circuit and to the base of the sixth transistor, which base is connected to the base of the second transistor so as to constitute a current mirror circuit, and an emitter connected to the second power source. In this case, it is possible to realize the second switch circuit with a simple circuit configuration.
It is preferable that the second bias circuit comprise a seventh transistor having a collector connected to the first power source via the second resistor and to the base of the seventh transistor, and an emitter connected to the collector of the sixth transistor. In this case, the second bias circuit can be realized with a simple circuit configuration.
Alternatively, the second bias circuit may comprise a third resistor having one end connected to the first power source via the second resistor and the other end connected to the collector of the sixth transistor. In this case also, the second bias circuit can be realized with a simple circuit configuration.
Moreover, it is preferable that the charge pump circuit further comprise a bias circuit for biasing the output node. In this case it is possible to maintain preferable balance between the charge current and the discharge current flowing to the output node.
Moreover, the bias circuit may comprise: a resistor having one end connected to the output node; and a DC power source having an anode connected to the other end of the resistor and a cathode connected to the second power source. In this case, the output node is biased by a DC power source. This enables to maintain preferable balance between the charge current and the discharge current flowing to the output node.
Alternatively, the bias circuit may comprise: a first resistor having one end connected to the first power source and the other end connected to the output node side; and a second resistor having one end connected to the second power source and the other end connected to the output node side. In this case, the output node is biased by resistance division, which enables to maintain a preferable balance between the charge current and the discharge current flowing to the output node.
Alternatively, the bias circuit may comprise: a bias transistor having a base connected to the output node and an emitter connected to the second power source; and a first resistor inserted between the collector of the bias transistor and the first power source, wherein a connection node between the first resistor and the bias transistor is connected to a subsequent stage output node positioned at a subsequent stage of the output node. In this case, by utilizing voltage between the base and the emitter of the bias transistor, it is possible to output a signal from the subsequent stage output node while the output node is biased. Moreover, because the bias circuit is constituted by a transistor having an emitter grounded, it is possible to convert a current output into voltage and increase the output range of the output signal from the subsequent stage output node from the power source voltage to the collector-emitter saturation voltage of the bias transistor.
Furthermore, the bias circuit having the aforementioned configuration may further comprise: a second resistor inserted between the output node and the base of the bias transistor; and a series circuit constituted by a third resistor and a capacitor inserted in a return path connecting a connection between the first resistor and the subsequent stage output node, with a connection between the base of the bias transistor and the second resistor. In this case, it is possible to obtain a bias circuit which also serves as a loop filter functioning as an active low pass filter.